Field of the Invention
The present disclosure relates generally to detecting and correcting errors associated with data stored in memory devices. In particular, the present disclosure is related to improving the access time and reliability of memory reads by a memory controller.
Description of the Related Art
Memory devices include internal, semiconductor, integrated circuits and/or external removable devices for use in computers or other electronic devices. Various types of memory exist, including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), flash memory, and others.
Flash memory devices can be utilized as volatile and/or non-volatile memory and typically include a one-transistor memory cell to allow for high memory densities, high reliability, and low power consumption. Some uses for flash memory include providing memory for solid state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players (e.g., MP3 players), movie players, and other electronic devices. In some cases, program code, user data, and/or system data (e.g., basic input/output system (BIOS) data to initialize and test the system hardware components and/or to load a boot loader or an operating system), may be stored in flash memory devices.
Two common types of flash memory array architectures include the “NAND” and “NOR” architectures. A NAND array architecture typically arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to (and in some cases form) an access line (e.g., a “word line”), with each memory cell of the array being coupled together in series between a common source and a data line (e.g., a “bit line”) in a “column” of the array. Additionally, the memory array may be accessed (e.g., for reads and writes to the array) by a NAND flash memory controller. The NAND flash memory and controller work in conjunction in order to increase performance of the NAND memory.
For example, the memory controller may include an error correcting code (ECC) component that allows for correction capability of data accessed via the memory. Various coding techniques, such as, utilization of low-density parity-check (LDPC) codes, trellis coded modulation (TCM), or the like, may be utilized by the ECC component to improve bit error rates (BERs) of the data stored via the flash memory. However, inclusion of these techniques may adversely affect the speed at which data may be retrieved.